Abstract

Basically Multiplication is the mathematical operation of scaling one number by another. Talking about today's engineering world, multiplication based operations are some of the frequently used Functions, currently implemented in many Digital Signal Processing (DSP) applications such as Convolution, Fast Fourier Transform, filtering and in Arithmetic Logic Unit (ALU) of Microprocessors. Since multiplication is such a frequently used operation, it's necessary for a multiplier to be fast and area efficient and so, development of a fast and low area multiplier has been a key area in which various improvisations have been experimented since digital era started. In this paper, an implementation of area efficient and reduced delay 64 bit Vedic Multiplier (VM) is proposed. To construct a 64x64 Vedic Multiplier, four 32x32 VMs and three 64-bit Ripple Carry Adders (RCAs) are required. But in proposed VM, instead of three 64-bit RCAs, only one 64-bit RCA and two proposed adders are used. In the proposed Adders, the area required for 64-bit RCA has been reduced, leading to a greater reduction in the logic delay. The proposed VM and conventional VM are coded in Verilog, synthesized and simulated using ISE simulator. It is implemented on the Xilinx Spartan6 family xc6slx150t-4fgg900 FPGA. The Area and logic delay of the proposed VM and conventional VM are compared